Partitioning and Reordering Techniques for Static Test Sequence Compaction of Sequential Circuits

Partitioning and Reordering Techniques for Static Test Sequence Compaction of Sequential Circuits Michael S. Hsiaoy and Srimat T. Chakradharyy yDepartment of Electrical and Computer Engineering, Rutgers University, Piscataway, NJ yyComputer & Communications Research Lab. NEC USA, Princeton, NJ Abstract We propose a new static test set compaction method based on a careful examination of attributes of fault coverage curves. Our method is based on two key ideas: (1) fault-list and testset partitioning, and (2) vector re-ordering. Typically, the rst few vectors of a test set detect a large number of faults. The remaining vectors usually constitute a large fraction of the test set, but these vectors are included to detect relatively few hard faults. We show that signi cant compaction can be achieved by partitioning faults into hard and easy faults. This signi cantly reduces the computational cost for static test set compaction without a ecting quality of compaction. The second technique re-orders vectors in a test set by moving sequences that detect hard faults to the beginning of the test set. Fault simulation of the newly concatenated re-ordered test set results in the omission of several vectors so that the compact test set is smaller than the original test set. Experiments on several ISCAS 89 sequential benchmark circuits and large production circuits show that our compaction procedure yields signi cant test set reductions in low execution times.